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  <title>[elecena] Dual UART with 16-byte FIFO and up to 5 Mbit/s Data Rate - zmiany ceny</title>
  <description>The NS16C2552 and NS16C2752 are dual channel Universal Asynchronous Receiver/Transmitter
		(DUART). The footprint and the functions are compatible to the PC16552D, while new features are
		added to the UART device. These features include low voltage support, 5V tolerant inputs, enhanced
		features, enhanced register set, and higher data rate.

	 The two serial channels are completely independent of each other, except for a common CPU
		interface and crystal input. On power-up both channels are functionally identical to the PC16552D.
		Each channel can operate with on-chip transmitter and receiver FIFO’s (in FIFO mode).

	 In the FIFO mode each channel is capable of buffering 16 bytes (for NS16C2552) or 64
		bytes (for NS16C2752) of data in both the transmitter and receiver. The receiver FIFO also has
		additional 3 bits of error data per location. All FIFO control logic is on-chip to minimize system
		software overhead and maximize system efficiency.

	 To improve the CPU processing bandwidth, the data transfers between the DUART and the CPU
		can be done using DMA controller. Signaling for DMA transfers is done through two pins per channel
		(TXRDY and RXRDY). The
		RXRDYfunction is multiplexed on one pin with the OUT2
		and BAUDOUT functions. The configuration is through Alternate Function Register.

	 The fundamental function of the UART is converting between parallel and serial data.
		Serial-to-parallel conversion is done on the UART receiver and parallel-to-serial conversion is
		done on the transmitter. The CPU can read the complete status of each channel at any time. Status
		information reported includes the type and condition of the transfer operations being performed by
		the DUART, as well as any error conditions (parity, overrun, framing, or break interrupt).

		
	 The NS16C2552 and NS16C2752 include one programmable baud rate generator for each
		channel. Each baud rate generator is capable of dividing the clock input by divisors of 1 to
		(216 - 1), and producing a 16X clock for driving the internal
		transmitter logic and for receiver sampling circuitry. The NS16C2552 and NS16C2752 have complete
		MODEM-control capability, and a processor-interrupt system. The interrupts can be programmed by the
		user to minimize the processing required to handle the communications link.</description>
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