The AD9467 is a 16-bit, monolithic, IF sampling analog-to-digital converter (ADC). It is optimized for high performance over wide bandwidths and ease of use. The product operates at a 250 MSPS conversion rate and is designed for wireless receivers, instrumentation, and test equipment that require a high dynamic range. The ADC requires 1.8 V and 3.3 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are LVDS compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances. A data clock output (DCO) for capturing data on the output is provided for signaling a new output bit. The internal power-down feature supported via the SPI typically consumes less than 5 mW when disabled. Optional features allow users to implement various selectable operating conditions, including input range, data format select, and output data test patterns. The AD9467 is available in a Pb-free, 72-lead, LFCSP specified over the −40°C to +85°C industrial temperature range. Product Highlights * IF optimization capability used to improve SFDR. * Outstanding SFDR performance for IF sampling applications such as multicarrier, multimode 3G, and 4G cellular base station receivers. * Ease of use: on-chip reference, high input impedance buffer, adjustable analog input range, and an output clock to simplify data capture. * Packaged in a Pb-free, 72-lead LFCSP package. * Clock duty cycle stabilizer (DCS) maintains overall ADC performance over a wide range of input clock pulse widths. * Standard serial port interface (SPI) supports various product features and functions, such as data formatting (offset binary, twos complement, or Gray coding). Applications * Multicarrier, multimode cellular receivers * Antenna array positioning * Power amplifier linearization * Broadband wireless * Radar * Infrared imaging * Communications instrumentation * 75.5 dBFS SNR to 210 MHz at 250 MSPS * 90 dBFS SFDR to 300 MHz at 250 MSPS * SFDR at 170 MHz at 250 MSPS * 92 dBFS at −1 dBFS * 100 dBFS at −2 dBFS * 60 fs rms jitter * Excellent linearity at 250 MSPS * DNL = ±0.5 LSB typical * INL = ±3.5 LSB typical * See data sheet for additional features https://elecena.pl/product/16954453/16-bit-200-msps-250-msps-analog-to-digital-converter 2020-06-07 https://elecena.pl/product/16954453/16-bit-200-msps-250-msps-analog-to-digital-converter 2025-01-18