The AD9981 is a complete, 10-bit, 95 MSPS, monolithic analog interface optimized for capturing YPbPr video and RGB graphics signals. Its 95 MSPS encode rate capability and full-power analog bandwidth of 200 MHz supports all HDTV video modes and graphics resolutions up to XGA (1024 × 768 at 85 Hz). The AD9981 includes a 95 MHz triple ADC with an internal reference, a PLL, programmable gain, offset, and clamp controls. The user provides only 3.3 V and 1.8 V power supplies and an analog input. Three-state CMOS outputs may be powered from 1.8 V to 3.3 V. The AD9981’s on-chip PLL generates a sample clock from the three-level sync (for YPbPr video) or the horizontal sync (for RGB graphics). Sample clock output frequencies range from 10 MHz to 95 MHz. PLL clock jitter is 9% or less p-p typical at 95 MSPS. With internal coast generation, the PLL maintains its output frequency in the absence of sync input. A 32-step sampling clock phase adjustment is provided. Output data, sync, and clock phase relationships are maintained. The auto-offset feature can be enabled to automatically restore the signal reference levels and to automatically calibrate out any offset differences between the three channels. The AD9981 also offers full sync processing for composite sync and sync-on-green applications. A clamp signal is generated internally or may be provided by the user through the CLAMP input pin. Fabricated in an advanced CMOS process, the AD9981 is provided in a space-saving, 80-pin, Pb-free, LQFP surface mount plastic package. It is specified over the 0°C to +70°C temperature range. APPLICATIONS * Advanced TVs * Plasma display panels * LCDTV * HDTV * RGB graphics processing * LCD monitors and projectors * Scan converters * 10-bit analog-to-digital converters * 95 MSPS maximum conversion rate * 9% or less p-p PLL clock jitter at 95 MSPS * Automated offset adjustment * 2:1 input mux * Power-down via dedicated pin or serial register