The ZL30622 is a fully compliant SEC (G.813) and EEC (G.8262) single channel Network Synchronizer with ultra-low jitter performance of 250fs RMS. ZL30622 comes in a tiny 5 x 5mm QFN package and is pin compatible with the ZL30151 line card PLL. The device accepts up to 3 input references and generates up to 3 differential or 6 single-ended CMOS output clocks . An integrated digital phase locked loop (DPLL) with programmable loop bandwidth from 0.1Hz to 500Hz provides G.8262 compliance including hitless reference switching, holdover and jitter filtering. An integrated fractional-N analog PLL (APLL) generates ultra-low jitter output clocks programmable to any frequency between <1Hz to 1035MHz. Click here for secure documentation