1 GHz SHARC+ DSP w/ Integrated Arm Cortex-A55

Reaching speeds of up to 1 GHz, the ADSP-SC598/SC596/SC595 processors are members of the ADSP-SC59x SHARC® family of products. Containing the same dual-SHARC+® DSP core architecture as the ADSP-SC594/SC592/SC591, these processors upgrade the integrated Arm core to a Cortex-A55 running at up to 1.2 GHz. The A55 processor, with FPU and Neon® DSP extensions, handles additional real-time processing tasks and manages peripherals used to interface to time-critical data in audio applications. These interfaces include Gigabit Ethernet, USB High-Speed, CAN FD, and a rich variety of other connectivity options for a flexible and simplified system design.

The ADSP-SC59x SHARC processors are members of the SIMD SHARC family of digital signal processors (DSPs) that feature Analog Devices, Inc., Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.

By integrating a rich set of industry-leading system peripherals and memory (see Table 1 in the data sheet), the SHARC+ processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.

Applications

* Automotive:

* audio amplifier, head unit, ANC/RNC, rear seat entertainment, digital cockpit, ADAS

* Consumer & Professional Audio:

* speakers, sound bars, AVRs, conferencing systems, mixing consoles, microphone arrays, headphones

* SHARC+ high performance floating-point core

* Up to 1000 MHz per SHARC+ core* 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache)* 32-bit, 40-bit, and 64-bit floating-point support * 32-bit fixed point * Byte, short word, word, long word addressed

* Arm Cortex-A55 core

* Up to 1200 MHz/3360 DMIPS with advanced SIMD and floating-point support* 32 kB L1 instruction cache with parity/32 kB L1 data cache with ECC* 256 kB L2 cache with ECC

* Powerful DMA system with 8 MemDMAs* On-chip memory protection* Integrated safety features

* 17 mm × 17 mm, 400-ball BGAED (0.8 mm pitch), RoHS compliant* Low system power across automotive temperature range