The ZL30145 is a highly integrated device that provides timing for line cards. The DPLL automatically locks to one input reference and provides two synchronized output clocks for synchronizing SONET/SDH and Synchronous Ethernet line cards. The ZL30145 has a on-chip digital phase-locked loop (DPLL) designed to provide rate conversion and jitter attenuation for Synchronous Ethernet, (SyncE), Synchronous Digital Hierarchy (SDH) and Synchronous Optical Network (SONET) networking equipment. The ZL30145 generates very low jitter clocks that meet the jitter requirements of ITU-T G.8262 Click here for secure documentation