The ZL30623 is a fully compliant SEC (G.813) and EEC (G.8262) dual channel Network Synchronizer with ultra-low jitter performance of 250fs RMS. The device accepts up to 6 input references and generates up to 6 differential or 12 single-ended CMOS output clocks . Dual, independent, digital phase locked loops (DPLLs) have programmable loop bandwidths from 0.1Hz to 500Hz and provide G.8262 compliance including hitless reference switching, holdover and jitter filtering. Dual, independent fractional-N analog PLLs (APLLs) generate ultra-low jitter output clocks programmable to any frequency between <1Hz to 1035MHz. Click here for secure documentation