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  <title>[elecena] High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor - zmiany ceny</title>
  <description>The MAX19588 is a 3.3V, high-speed, high-performance
analog-to-digital converter (ADC) featuring a
fully differential wideband track-and-hold (T/H) and a
16-bit converter core. The MAX19588 is optimized for
multichannel, multimode receivers, which require the
ADC to meet very stringent dynamic performance
requirements. With a -82dBFS noise floor, the
MAX19588 allows for the design of receivers with superior
sensitivity requirements.

At 100Msps, the MAX19588 achieves a 79dB signal-to-noise
ratio (SNR) and an 82.1dBc/97.7dBc single-tone
spurious-free dynamic range performance
(SFDR1/SFDR2) at fIN = 70MHz. The MAX19588 is not
only optimized for excellent dynamic performance in
the 2nd Nyquist region, but also for high-IF input frequencies.
For instance, at 130MHz, the MAX19588
achieves an 82.3dBc SFDR and its SNR performance
stays flat (within 2.3dB) up to 175MHz. This level of performance
makes the part ideal for high-performance
digital receivers.

The MAX19588 operates from a 3.3V analog supply
voltage and a 1.8V digital voltage, features a 2.56VP-P
full-scale input range, and allows for a guaranteed sampling
speed of up to 100Msps. The input track-and-hold
stage operates with a 600MHz full-scale, full-power
bandwidth.

The MAX19588 features parallel, low-voltage CMOS-compatible
outputs in two's-complement output format.

The MAX19588 is manufactured in an 8mm x 8mm,
56-pin thin QFN package with exposed paddle (EP) for
low thermal resistance, and is specified for the extended
industrial (-40°C to +85°C) temperature range.

Applications

* Antenna Array Processing
* Cellular Base-Station Transceiver Systems (BTS)
* E911 Location Receivers
* High-Performance Instrumentation
* Multicarrier Receivers
* Multistandard Receivers
* Wireless Local Loop (WLL)

* 100Msps Conversion Rate

* -82dBFS Noise Floor

* Excellent Low-Noise Characteristics

* SNR = 79.4dB at fIN = 10MHz

* SNR = 79dB at fIN = 70MHz

* Excellent Dynamic Range (SFDR1/SFDR2)

* 93.2dBc/102.5dBc at fIN = 10MHz

* 82.1dBc/97.7dBc at fIN = 70MHz

* Less than 0.1ps Sampling Jitter

* 1275mW Power Dissipation

* 2.56VP-P Fully Differential Analog Input Voltage Range

* CMOS-Compatible Two's-Complement Data Output

* Separate Data Valid Clock and Over-Range Outputs

* Flexible Input Clock Buffer

* Small 56-Pin, 8mm x 8mm x 0.8mm Thin QFN Package

* EV Kit Available for MAX19588 (Order MAX19588EVKIT)</description>
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