The MAX5270 contains eight 13-bit, voltage-output digital-to-analog converters (DACs). On-chip precision output amplifiers provide the voltage outputs. The device operates from +12V/-12V supplies. Its output voltage swing ranges from 0V to +8.192V and is achieved with no external components. The MAX5270 has three pairs of differential reference inputs; two of these pairs are connected to two DACs each, and a third pair is connected to four DACs. The references are independently controlled, providing different full-scale output voltages to the respective DACs. The MAX5270 operates within the following voltage ranges: VDD = +11.4V to +12.6V, VSS = -11.4V to -12.6V, and VCC = +4.75V to +5.25V. The MAX5270 features double-buffered interface logic with a 13-bit parallel data bus. Each DAC has an input latch and a DAC latch. Data in the DAC latch sets the output voltage. The eight input latches are addressed with three address lines. Data is loaded to the input latch with a single write instruction. An asynchronous load input (active-low LD) transfers data from the input latch to the DAC latch. The active-low LD input controls all DACs; therefore, all DACs can be updated simultaneously by asserting the LD-bar pin. An asynchronous active-low CLR input sets the output of all eight DACs to the respective DUTGND input of the op amp. Note that active-low CLR is a CMOS input, which is powered by VDD. All other logic inputs are TTL/CMOS compatible. The "A" grade of the MAX5270 has a maximum INL of ±2LSBs, while the "B" grade has a maximum INL of ±4LSBs. Both grades are available in 44-pin MQFP packages. Applications * Arbitrary Function Generators * Automated Test Equipment (ATE) * Avionics and Military Systems * Digital Gain and Offset Control * Industrial Process Controls * Minimum Component Count Analog Systems * SONET Applications * Full 13-Bit Performance Without Adjustments * 8 DACs in a Single Package * Buffered Voltage Outputs * Voltage Swing Between 0V and 8.192V * 22µs Output Settling Time * Drives up to 10,000pF Capacitive Load * Low Output Glitch: 30mV * Low Power Consumption: 10mA (typ) * Small Package: 44-Pin MQFP * Double-Buffered Digital Inputs * Asynchronous Load Updates All DACs Simultaneously * Asynchronous CLR-bar Forces All DACs to DUTGND Potential