The MAX533 serial-input, voltage-output, 8-bit quad digital-to-analog converter (DAC) operates from a sin-gle +2.7V to +3.6V supply. Internal precision buffers swing rail to rail, and the reference input range includes both ground and the positive rail. The MAX533 features a 1µA shutdown mode. The serial interface is double buffered: a 12-bit input shift register is followed by four 8-bit buffer registers and four 8-bit DAC registers. The 12-bit serial word consists of eight data bits and four control bits (for DAC selection and special programming commands). Both the input and DAC registers can be updated indepen-dently or simultaneously with a single software com-mand. Two additional asynchronous control pins, active-low LDAC and active-low CLR, provide simultaneous updating or clearing of the input and DAC registers. The interface is compatible with SPI™, QSPI™ (CPOL = CPHA = 0 or CPOL = CPHA = 1), and Microwire™. A buffered data output allows daisy chaining of serial devices. In addition to 16-pin DIP and CERDIP packages, the MAX533 is available in a 16-pin QSOP that occupies the same area as an 8-pin SO. Applications * Digital Gain and Offset Control * Portable Instrumentation * Programmable Attenuators * Programmable Current Sources * +2.7V to +3.6V Single-Supply Operation * Ultra-Low Supply Current: * 0.7mA while Operating * 1µA in Shutdown Mode * Ultra-Small 16-Pin QSOP Package * Ground to VDD Reference Input Range * Output Buffer Amplifiers Swing Rail to Rail * 10MHz Serial Interface, Compatible with SPI, QSPI * (CPOL = CPHA = 0 or CPOL = CPHA = 1), and Microwire * Double-Buffered Registers for Synchronous Updating * Serial Data Output for Daisy Chaining * Power-On Reset Clears Serial Interface and Sets All Registers to Zero * Software Shutdown * Software-Programmable Logic Output * Asynchronous Hardware Clear Resets All Internal Registers to Zero https://elecena.pl/product/22328804/2-7v-low-power-8-bit-quad-dac-with-rail-to-rail-output-buffers 2022-12-28 https://elecena.pl/product/22328804/2-7v-low-power-8-bit-quad-dac-with-rail-to-rail-output-buffers 2025-01-20