The LTC3718 is a high current, high efficiency synchronous switching regulator controller for DDR and QDR™ memory termination. It operates from an input as low as 1.5V and provides a regulated output voltage equal to (0.5)VIN. The controller uses a valley current control architecture to enable high frequency operation with very low on-times without requiring a sense resistor. Operating frequency is selected by an external resistor and is compensated for variations in VIN and VOUT. The LTC3718 uses a pair of standard 5V logic level N-channel external MOSFETs, eliminating the need for expensive P-channel or low threshold devices. Forced continuous operation reduces noise and RF interference. Fault protection is provided by internal foldback current limiting, an output overvoltage comparator and an optional short-circuit timer. Soft-start capability for supply sequencing can be accomplished using an external timing capacitor. OPTI-LOOP® compensation allows the transient response to be optimized over a wide range of loads and output capacitors. Applications * Bus Termination: DDR/QDR Memory, SSTL, HSTL,... * Servers, RAID Systems * Distributed Power Systems * Synchronous Buck with General Purpose Boost * Very Low VIN(MIN): 1.5V * Ultrafast Transient Response * True Current Mode Control * 5V Drive for N-Channel MOSFETs Eliminates Auxillary 5V Supply * No Sense Resistor Required * Uses Standard 5V Logic-Level N-Channel MOSFETs * VOUT(MIN): 0.4V * VOUT Tracks 1/2 VIN or External VREF * Symmetrical Source and Sink Output Current Limit * Adjustable Switching Frequency * tON(MIN) <100ns * Power Good Output Voltage Monitor * Programmable Soft-Start * Output Overvoltage Protection * Optional Short-Circuit Shutdown Timer * Small 24-Lead SSOP Package https://elecena.pl/product/259104/low-input-voltage-dc-dc-controller-for-ddr-qdr-memory-termination 2007-03-04 https://elecena.pl/product/259104/low-input-voltage-dc-dc-controller-for-ddr-qdr-memory-termination 2014-04-18 https://elecena.pl/product/259104/low-input-voltage-dc-dc-controller-for-ddr-qdr-memory-termination 2025-01-18