This design includes 8085 CPU, 8251 USART, 32 KiB SRAM, 32 KiB or 16 KiB ROM. It uses a GAL16V8/ATF16V8 simple programmable logic device (SPLD) instead of discrete logic ICs for the address decode and the frequency divider for USART. It reduces the number of components, allows for tweaking the configuration by re-programming the SPLD, and provides an introduction to the programmable logic devices. Specifications 80C85A or 8085A CPU, 3.072 MHz or 4.9152 MHz CPU clock frequency 82C51A or 8251A USART for console connection 32 KiB of battery backed SRAM Up to 32 KiB of ROM. EEPROM, UV EPROM or Flash ROM memory is supported 40-pin extension bus connector, including most of 8085 signals and demultiplexed data and address buses You can find almost all the components to build this computer in my webshop. This is the project page: https://www.retrobrewcomputers.org/doku.php?id=boards:sbc:minimax8085:start Schema: mini8085-schematic-1.0