The IDT650-27 is a low cost, low-jitter, high-performance clock synthesizer for networking applications. Using analog Phase Locked Loop (PLL) techniques, the device accepts a 12.5 MHz or 25 MHz clock or fundamental mode crystal input to produce multiple output clocks for networking chips, PCI devices, SDRAM, and ASIDT. The IDT650-27 outputs all have zero ppm synthesis error. The IDT650-27 is pin compatible and functionally equivalent to the IDT650-07. It is a performance upgrade and is recommended for all new 3.3 V designs. See the MK74CB214, IDT551, and IDT552-01 for non-PLL buffer devices which produce multiple low-skew copies of these output clocks. See the IDT570, IDT9112-16/17/18 for zero delay buffers that can synchronize outputs and other needed clocks.