The 9DB233 zero delay buffer (ZDB) supports PCIe Gen3 requirements while being backward compatible with PCIe Gen2 and Gen1. The 9DB233 is driven by a differential SRC output pair from a 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without spread spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while two clock request (OE#) pins make the 9DB233 suitable for Express Card applications.