The 72V2111 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, Read Clock (RCLK) or Write Clock (WCLK), is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short; the variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.