The 72V3612 is a 3.3V version of the 723612. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip buffer data in opposite directions. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. The enables for each port are arranged to provide a simple bi-directional interface between microprocessors and/or buses with synchronous control.