The 71V632 3.3V CMOS SRAM is organized as 64K x 32. The pipelined burst architecture provides cost-effective 3-1-1-1 secondary cache performance for processors up to 117MHz. The 71V632 SRAM contains write, data, address, and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.