The LMK5B12204 is high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of Ethernet-based networking applications. The device integrates one DPLL and two APLLs to provide hitless switching and jitter attenuation using the programmable loop bandwidths (LBWs) with one external loop filter capacitor to maximize the flexibility and ease of use. APLL1 features an ultra-high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology in VCO1 and can generate 312.5MHz output clocks with 50fs typical RMS jitter (12kHz to 20MHz) irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 features a conventional LC VCO to provide options for a second frequency and/or synchronization domain. The integrated EEPROM can be used for custom system configurations on start-up. Internal LDO regulators provide excellent power supply noise rejection (PSNR) to reduce the cost and complexity of the power delivery network.