ADC12QJ1600-SEP is a quad channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the device suited for a variety of mulch-chanel communications systems. Full-power input bandwidth (-3 dB) of 6 GHz enables direct RF sampling of L-band and S-band. A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems. JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.