8-bit shift register designed for 2.0 V to 5.5 V VCC operation. The device contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks (RCLK, SRCLK) and direct overriding clear ( ̅R̅̅C̅̅L̅̅R̅ , ̅S̅̅R̅̅C̅̅L̅̅R̅ ) inputs are provided on the shift and storage registers. A serial output (QH’) is provided for cascading purposes. The shift-register (SRCLK) and storage-register (RCLK) clocks are positive-edge triggered. If the clocks are tied together, the shift register always is one clock pulse ahead of the storage register.