Fanout Buffer, Equalizer Receiver, 10 Gbps, 1.8 V / 2.5 V, with 1:6 Differential CML Outputs

The NB7VQ1006M is a high performance EQualizer Receiver (signal enhancer) that operates up to 10 Gbps/7.5 GHz with a 1.8 V or 2.5 V power supply. When placed in series with a Data/Clock path, it will enhance the degraded signal transmitted across a FR4 backplane or cable interconnect and output six identical CML copies of the input signal. The EQualizer ENable pin (EQEN) allows the IN/IN inputs to either flow through or bypass the EQualizer section. Control of the EQualizer function is realized by setting EQEN. When EQEN is set Low, the IN / IN inputs bypass the Equalizer. When EQEN is set High, the IN / IN inputs flow through the EQualizer. The default state at start-up is LOW. The differential Data/Clock inputs incorporate a pair of internal 50-ohm termination resistors, in a 100-ohm center-tapped configuration, via the VT Pin and will accept differential LVPECL, CML or LVDS logic levels. This feature provides transmission line termination on-chip, at the receiver end, eliminating external components. The NB7VQ1006M is a member of the PEEQ GigaComm™ family of high performance Data/Clock products.