The NB3F8L3005C is a 2:1:5 Clock / Data fanout buffer operatingon a 3.3 V / 2.5 V Core VDD and two flexible 3.3 V / 2.5 V / 1.8 V /1.5 V VDDOx supplies which must be equal or less than VDD.A Mux selects between a Crystal input, or a differential/SE Clock /Data inputs. Differential Inputs accept LVPECL, LVDS, HCSL, orSSTL and Single−Ended levels. The MUX control line, SEL selectsCLK/CLK, or Crystal input pins per Table 3. The Crystal input isdisabled when a Clock input is selected. Output enable pin, OE,synchronously forces a High Impedance state (Hi−Z) when Low perTable 4.Outputs consist of five single−ended LVCMOS outputs.