The HEF40175B is a quad positive edge triggered D-type flip-flop with four data (Dn) inputs, common clock (CP) and asynchronous master reset (MR) inputs, and complementary Qn and Qn outputs. When MR is HIGH data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. When LOW, MR resets all flip-flops (Qn = LOW, Qn = HIGH), independent of CP and Dn. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD.