The 74ABT16841A Bus interface latch is designed to provide extra data width for wider data/address paths of buses carrying parity. The 74ABT16841A consists of two sets of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (nLE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the nLE HIGH-to-LOW transition, the data that meets the set-up and hold time is latched. Data appears on the bus when the Output Enable (nOE) is LOW. When nOE is HIGH the output is in the high-impedance state.