CY7C1665KV18-550BZXC is a 144-Mbit (4 M × 36) QDR II+ synchronous pipelined SRAM with separate DDR read and write ports. It supports 550 MHz clock operation (1100 MHz data transfer) with four-word burst and 2.5-cycle read latency (DOFF high), or QDR I mode with 1-cycle latency (DOFF low). It uses 1.8 V core with 1.4 V to VDDQ I/O, echo clocks (CQ/CQ) and QVLD for data capture, plus IEEE 1149.1 JTAG.