CY7C1663KV18-550BZXC is a 144-Mbit (8 M × 18) QDR II+ synchronous pipelined SRAM with separate read and write ports and a four-word burst architecture. It supports a 550 MHz clock with DDR transfers (1100 MHz data rate) and 2.5-cycle read latency. The device operates from 1.7–1.9 V VDD with 1.4 V–VDD VDDQ and is offered in a 165-ball Pb-free FBGA package for high-bandwidth networking, DSP, and packet buffering.