CY7C1650KV18-450BZC is a 144-Mbit DDR II+ synchronous pipelined SRAM organized as 4 M × 36 with two-word burst. It supports 450 MHz maximum clock and DDR data transfers at 900 MHz, with 2.0-cycle read latency (or 1 cycle when DOFF is low). Core VDD is 1.7 V to 1.9 V and I/O VDDQ is 1.4 V to VDD. It includes CQ/CQ echo clocks, QVLD data-valid, ZQ impedance match, and IEEE 1149.1 JTAG.