The CY7C1645KV18-400BZXI is a 144-Mbit QDR II+ synchronous pipelined SRAM organized as 4 M × 36 with separate read and write ports to eliminate data-bus turnarounds. It supports four-word burst transfers with 2-cycle read latency (or 1-cycle QDR I mode via DOFF), DDR I/O at up to 400 MHz clock (800 MT/s), echo clocks and QVLD, HSTL I/Os, and an on-chip PLL (120 MHz to max freq), plus JTAG 1149.1.