CY7C1613KV18-300BZXC is a 144-Mbit QDR II synchronous pipelined burst SRAM organized as 8 M × 18 with separate read and write ports to eliminate bus turnarounds. It supports four-word bursts and DDR transfers (data at 600 MHz with a 300 MHz clock). Core VDD is 1.8 V ±0.1 V with VDDQ from 1.4 V to VDD, 165-ball FBGA package, and selectable 1.5-cycle or 1-cycle read latency via DOFF.