CY7C1612KV18-250BZXI is a 144-Mbit QDR II synchronous pipelined SRAM organized as 8M × 18, with independent read and write ports for concurrent transactions and no bus turnaround. It supports two-word bursts and DDR interfaces, operating to 250 MHz clock. Read latency is 1.5 cycles with DOFF high (1 cycle in QDR I mode). Core supply is 1.8 V (±0.1 V) with VDDQ from 1.4 V to VDD, in a 165-ball FBGA.