The CY7C2665KV18-550BZXI is a 144-Mbit QDR II+ synchronous pipelined SRAM organized as 4M × 36 with four-word burst (4 × 36) transfers in two clock cycles. It supports separate read and write ports with DDR interfaces on both ports (data at 1100 MHz) using a 550 MHz clock, with 2.5-cycle read latency (DOFF high) or 1-cycle QDR I mode (DOFF low). 1.8 V core with VDDQ 1.4 V to VDD, ODT and PLL, in 165-ball Pb-free FBGA, industrial range.