CY7C2665KV18-550BZXC is a 144-Mbit QDR II+ synchronous pipelined SRAM in a 4M × 36 organization with separate read and write ports for concurrent transactions. It runs up to 550 MHz clock with DDR I/O (1100 MHz data transfer) and a four-word burst with 2.5-cycle read latency. Core VDD is 1.7 V to 1.9 V and VDDQ is 1.4 V to VDD. It is offered in a 165-ball FBGA Pb-free package with on-die termination.