CY7C2665KV18-450BZI is a 144-Mbit QDR II+ synchronous pipelined SRAM in 4M × 36, using separate read and write ports with DDR interfaces for concurrent transactions. It supports 450 MHz clock operation, 2.5-cycle read latency (1-cycle when DOFF is low), four-word burst, echo clocks (CQ/CQ) and QVLD data-valid. Core VDD is 1.7 V to 1.9 V with VDDQ 1.4 V to VDD, in a 165-ball FBGA, -40°C to +85°C.