CY7C2663KV18-550BZXC is a 144-Mbit QDR II+ synchronous pipelined SRAM in an 8M × 18 organization. It uses separate read and write ports with DDR I/O and a four-word burst, supporting a 550 MHz clock (1100 MHz data transfer) with 2.5-cycle read latency. Core VDD is 1.8 V (1.7–1.9 V) with VDDQ from 1.4 V to VDD, and it integrates ODT and echo clocks (CQ/CQ) for high-speed capture and timing.