CY7C2663KV18-550BZI is a 144-Mbit QDR II+ synchronous pipelined SRAM (8M × 18) with independent read and write ports for concurrent transactions. It supports a 550 MHz clock with DDR transfers at 1100 MHz, 2.5-cycle read latency (or 1-cycle with DOFF low), and integrates on-die termination, echo clocks, and QVLD for capture timing. Core VDD is 1.7–1.9 V and VDDQ is 1.4 V to VDD.