CY7C2663KV18-450BZXC is a 144-Mbit QDR® II+ synchronous pipelined SRAM (8M × 18) with separate read and write ports for concurrent transactions and no bus turnaround. It supports four-word burst transfers with 2.5-cycle read latency, DDR data at 1100 MHz using a 450 MHz clock. It runs from 1.8 V core with 1.4 V to VDD I/O, integrates echo clocks, QVLD, PLL, and on-die termination, in a 165-ball FBGA Pb-free package.