CY7C2644KV18-300BZXI is a 144-Mbit QDR II+ synchronous pipelined SRAM with separate read and write ports and a two-word burst architecture. It transfers data on both edges of K/K clocks (DDR, 500 MHz at 250 MHz) with 2.0-cycle read latency, echo clocks (CQ/CQ), QVLD, and on-die termination for D, BWS, and K/K. It runs from 1.8 V core (VDD 1.7–1.9 V) and 1.4 V to VDD I/O (VDDQ), in a 165-ball CCGA.