CY7C25702KV18-550BZXI is a 72-Mbit DDR II+ synchronous pipelined SRAM (2M × 36) with two-word burst architecture. It supports up to 550 MHz clock with 1100 MHz DDR data transfers and 2.5-cycle read latency (DOFF HIGH). Dual input clocks (K/K), echo clocks (CQ/CQ), QVLD data-valid, and IEEE 1149.1 JTAG aid high-speed capture and test. Supplies: 1.7 V to 1.9 V VDD, 1.4 V to VDD VDDQ, with on-die termination.