CY7C25652KV18-550BZXC is a 72-Mbit QDR II+ synchronous pipelined SRAM (2M × 36) with separate read and write DDR ports to support concurrent transactions. It runs up to 550 MHz (1100 MHz data rate) with 2.5-cycle read latency, using 1.8 V core (1.7 V to 1.9 V) and 1.4 V to VDD I/O supplies. On-die termination, echo clocks, QVLD, and an on-chip PLL aid high-speed timing in a 165-ball Pb-free FBGA.