CY7C25632KV18-550BZXI is a 72-Mbit QDR II+ synchronous pipelined SRAM organized as 4M × 18 with independent read and write ports for concurrent transactions. It supports four-word bursts with 2.5-cycle read latency, a 550 MHz clock (DDR data at 1100 MHz), and 1.8 V core with VDDQ from 1.4 V to VDD. ODT, programmable output impedance via ZQ/RQ, echo clocks and QVLD, and a PLL (120 MHz to max) aid high-speed capture.