CY7C25632KV18-500BZXC is a 72-Mbit QDR II+ synchronous pipelined SRAM in a 165-ball FBGA package, organized as 4M × 18 with separate read and write DDR ports for concurrent transactions. It supports up to 500 MHz clock (1.0 GHz data transfer), four-word burst, 2.5-cycle read latency (DOFF HIGH), on-die termination for D/BWS/K, and PLL-based timing. VDD 1.7–1.9 V; VDDQ 1.4 V to VDD.