CY7C1515KV18-300BZI is a 72-Mbit QDR II synchronous pipelined SRAM organized as 2M × 36, with separate read and write ports and a four-word burst (four 36-bit transfers in two cycles). It supports 300 MHz clocks with DDR I/O and echo clocks (CQ/CQ) for capture. Read latency is 1.5 cycles with DOFF HIGH or 1 cycle in QDR I mode (DOFF LOW). Industrial 165-ball FBGA, core VDD 1.8 V.