CY7C1515KV18-300BZCT is a 72-Mbit QDR II synchronous pipelined SRAM (2M × 36) with independent read/write ports and a four-word burst architecture. It supports DDR transfers on both ports at up to 300 MHz clock, uses K/K input clocks and C/C output clocks with echo CQ/CQ, and offers 1.5-cycle read latency with DOFF HIGH (1-cycle QDR I mode with DOFF LOW). Core VDD is 1.8 V ±0.1 V with 1.4 V to VDD I/O VDDQ.