CY7C1514KV18-300BZXI is a 1.8 V QDR II synchronous pipelined SRAM organized as 2M × 36 (72 Mbit). It uses separate read and write ports with DDR interfaces and a two-word burst, eliminating bus turnaround and enabling concurrent transactions. Rated for 300 MHz clock operation, it supports single clock mode, echo clocks (CQ/CQ), and 1.5-cycle read latency with DOFF HIGH (1-cycle QDR I mode with DOFF LOW).