CY7C1512KV18-300BZXI is a 72-Mbit QDR II synchronous pipelined SRAM in a 4M × 18 organization with separate read and write ports to eliminate bus turnaround and support concurrent transactions. It uses DDR interfaces with two-word burst and runs up to 300 MHz. Core supply is 1.8 V (1.7 V to 1.9 V) with 1.4 V to VDDQ I/O. HSTL output buffers, PLL, echo clocks, and IEEE 1149.1 JTAG are supported.