CY7C1512KV18-300BZXC is a 72-Mbit QDR II synchronous pipelined SRAM organized as 4M × 18, with independent read and write ports and two-word burst transfers. It supports DDR I/O for data transfer at 600 MHz with a 300 MHz clock, 1.8 V core supply, and VDDQ from 1.4 V to VDD. It includes 1.5-cycle read latency (DOFF HIGH), byte writes, echo clocks, on-chip PLL, JTAG, and programmable output impedance.