CY7C1512KV18-250BZXI is a 72-Mbit QDR II SRAM organized as 4M × 18 with separate read and write ports for concurrent transactions and two-word burst transfers. It uses DDR interfaces with input clocks K/K and output clocks C/C, plus echo clocks CQ/CQ for data capture, and supports up to 250 MHz. Read latency is 1.5 cycles with DOFF HIGH or 1 cycle in QDR I mode. Core VDD is 1.8 V and VDDQ is 1.4 V to VDD.