CY7C1470BV25-200AXC is a 2.5 V, 72-Mbit (2M × 36) synchronous pipelined burst SRAM with No Bus Latency (NoBL) architecture for zero-wait-state back-to-back reads/writes. It supports 200 MHz bus operation, linear or interleaved 4-beat bursts via an on-chip counter, fully registered inputs/outputs, and byte writes via BWa–BWd. Asserting ZZ enters sleep mode with data integrity guaranteed.