CY7C1520KV18-250BZCT is a 72-Mbit (2M × 36) synchronous pipelined DDR-II SRAM with two-word burst operation. It supports up to 250 MHz clocking (DDR transfers at 500 MHz) and selectable read latency: 1.5 cycles with PLL enabled (DOFF HIGH) or 1 cycle DDR-I mode with DOFF LOW. HSTL I/Os support 1.5 V/1.8 V VDDQ, with echo clocks (CQ/CQ), ZQ impedance match, and JTAG 1149.1 test access.