The AD9960 is a member of the MxFE family, a group of integrated mixed-signal front-end ICs optimized for specific communications markets. The AD9960 has been optimized for high performance, wireless applications using a half-duplex protocol. In the Rx signal path, the AD9960 integrates a dual simultane-ous sampling SHA followed by a 14-bit muxed input ADC with 32 MSPS per channel capabilities. On the Tx signal path, it integrates a dual 12-bit, 32 MSPS TxDAC®. The power bias of the ADC and DACs can be reduced to support low power operation modes. The AD9960 uses a single input clock pin (CLKIN) to generate all internal clocks with an optional clock doubler to generate the ADC sampling clock. Both the Rx and Tx signal paths provide CIC and programma-ble FIR filters with selectable decimation/interpolation factors to reduce the DSP processing and analog filtering requirements. A flexible bidirectional 16-bit data port is used to interface to popular DSPs. The bus direction is controlled via the DSP with the AD9960 generating a frame sync pulse indicating when valid interleaved Rx data begins to appear on the bus or when the DSP can place valid complex or real Tx data on to the bus. GPIO pins are available to support different DSP requirements. The AD9960 also integrates auxiliary functions accessible via serial programmable interface (SPI) registers. Three muxed-input ADCs provide the ability to monitor up to 10 channels, while two voltage DACs can be used for control purposes. The full-scale input/output levels of each of these 10-bit resolution converters are also individually programmable. Also included are nine GPIO pins that are SPI-configurable. A 3- or 4- wire SPI is used to configure the AD9960’s many modes of operation. The AD9960 is packaged in an 80-lead LQFP (low profile quad flat package) and is specified over the −40°C to +85°C tempera-ture range. APPLICATIONS * RFID readers * Receive path includes * Simultaneous sampling 32 MSPS I/Q SHA * 64 MSPS 14-bit muxed ADC with 77 dBFS SNR * Bypassable 2nd order CIC and 64-tap FIR decimation filters * Transmit path includes * Dual 12-bit, 32 MSPS TxDAC * Bypassable 64-tap FIR and 3rd order CIC decimation filters * Auxiliary converters includes * Dual 10-bit voltage output DACs * Three 10-bit SAR muxed ADCs—10 analog inputs * Programmable full-scale input/output levels